`timescale 1ns / 1ps

module ram_32x1024_burst #(
    parameter DATA_WIDTH = 128,
    parameter ADDR_WIDTH = 10,
    parameter DEPTH = 256 // ??????256???????????? ???????
)(
    input wire clk,
    input wire rst_n,
    //AXI
    input wire we,
    //input wire re,
    input wire [ADDR_WIDTH-1:0] addr,
    input wire [DATA_WIDTH-1:0] din,
    input wire [7:0] burst_len,
    
    output reg [DATA_WIDTH-1:0] dout,
    output reg burst_done,
    output reg burst_last
);

    reg [DATA_WIDTH-1:0] ram [0:DEPTH-1];

    reg [7:0] write_counter;

    reg read_active;
    reg [7:0] read_counter;
    
    // ??????
        integer i;
        always @(posedge clk or negedge rst_n) begin
            if (!rst_n) begin
                for (i = 0; i < DEPTH; i = i + 1)
                    ram[i] <= 0;
            end
        end

    //?????
        always @(posedge clk or negedge rst_n) begin
            if (!rst_n) begin
                write_counter <= 8'b0;
                burst_done    <= 1'b0;
                burst_last    <= 1'b0;
            end else begin
                if (we) begin
                    if (write_counter < burst_len) begin
                        ram[addr + write_counter] <= din;
                        write_counter <= write_counter + 1;
                    end 
                    if (write_counter == burst_len - 1) begin
                        burst_last    <= 1'b1;
                    end else begin
                        burst_last    <= 1'b0;
                    end
                    if (write_counter == burst_len) begin
                        burst_done    <= 1'b1;
                    end else begin
                        burst_done    <= 1'b0;
                    end
                end
            end
        end

    //?????
/*         always @(posedge clk or negedge rst_n) begin
            if (!rst_n) begin
                read_active  <= 1'b0;
                read_counter <= 8'b0;
                dout         <= '0;
            end else begin
                if (re && !read_active) begin
                    read_active  <= 1'b1;
                    read_counter <= 8'b0;
                    dout <= ram[addr];
                end
                else if (read_active) begin
                    if (read_counter < burst_len) begin
                        read_counter <= read_counter + 1;
                        dout <= ram[addr + read_counter];
                    end else begin
                        read_active <= 1'b0;
                        dout <= '0;
                    end
                end else begin
                    dout <= '0;
                end
            end
        end */
endmodule